1. Field of the Invention
This invention relates generally to circuits for driving electronic displays, and more particularly to a system and method for using an internal sequencer to sequentially drive the word lines of a display.
2. Description of the Background Art
FIG. 1 shows a prior art display driver circuit 100, for driving a display 102, which includes an array of pixel cells arranged in 768 rows and 1024 columns. Display driver circuit 100 includes row decoder 104, write hold register 106, pointer 108, instruction decoder 110, invert logic 112, timing generator 114, and input buffers 116, 118, and 120. Driver circuit 100 receives clock signals via SCLK terminal 122, invert signals via invert (INV) terminal 124, data and addresses via 32-bit system data bus 126, and operating instructions via 2-bit op-code bus 128, all from a system (e.g., a computer) not shown. Timing generator 114 generates timing signals, by methods well known to those skilled in the art, and provides these timing signals to the components of driver circuit 100 via clock signal lines (not shown), to coordinate the operation of each of the components.
Invert logic 112 receives the invert signals from the system via INV terminal 124 and buffer 116, and receives the data and addresses from the system via system data bus 126 and buffer 118. Responsive to a first invert signal (INV), invert logic 112 asserts the received data and addresses on a 32-bit internal data bus 130. Responsive to a second invert signal (INV), invert logic 112 asserts the complement of the received data on internal data bus 130. Internal data bus 130 provides the asserted data to write hold register 106, and provides the asserted row addresses (via 10 of its 32 lines) to row decoder 104.
Instruction decoder 110 receives op-code instructions from the system, via op-code bus 128 and buffer 120, and, responsive to the received instructions, provides control signals, via an internal control bus 132, to row decoder 104, write hold register 106, and pointer 108. Responsive to the system asserting data on system data bus 126 and a first instruction (i.e., Data Write) on op-code bus 128, instruction decoder 110 asserts control signals on control bus 132, causing write hold register 106 to load the asserted data via internal data bus 130 into a first portion of write hold register 106. Because internal data bus 130 is only 32 bits wide, 32 data write commands are necessary to load an entire line (1024 bits) of data into write hold register 106. Pointer 108 provides an address, via a set of lines 134, which indicates the portion of write hold register 106 to which the data is to be written. As each successive Data Write command is executed, pointer 108 increments the address asserted on lines 134 to indicate the next 32-bit portion of write hold register 106.
Responsive to the system asserting a row address on system data bus 126 and a second instruction (i.e., load row address) on op-code bus 128, instruction decoder 110 asserts control signals on control bus 132 causing row decoder 104 to store the asserted row address. Then, responsive to the system asserting a third instruction (i.e., Array Write) on op-code bus 128, instruction decoder 110 asserts control signals on control bus 132, causing write hold register 106 to assert the 1024 bits of stored data on a set of 1024 data output terminals 136, and causing row decoder 104 to decode the stored row address and assert a write signal on one of a set of 768 word-lines 138 corresponding to the decoded row address. The write signal on the corresponding word-line causes the data being asserted on data output terminals 136 to be latched into a corresponding row of pixel cells (not shown in FIG. 1) of display 102.
Those skilled in the art will recognize that write hold register 106, pointer 108, invert logic 112, and buffers 116 and 118 function together as data processing means 150 for receiving data from the system, accumulating and formatting the data, and providing the data to display 102. Row decoder 104 functions as row selecting means 160 for selecting a row of display 102 to which the data provided by data processing means 150 is to be written. Instruction decoder 110 functions as instruction means for receiving op-code instructions from the system, and controlling and coordinating data processing means 150 and row selecting means 160 responsive to the received op-code instructions.
FIG. 2 shows an exemplary pixel cell 200(r,c) of display 100, where (r) and (c) indicate the row and column of the pixel cell, respectively. Pixel cell 200 includes a latch 202, a pixel electrode 204, and switching transistors 206 and 208. Latch 202 is a static random access memory (SRAM) latch. One input of latch 202 is coupled, via transistor 206, to a Bit+ data line 210(c), and the other input of latch 202 is coupled, via transistor 208 to a Bit- data line 212(c). The gate terminals of transistors 206 and 208 are coupled to word line 138(r). An output terminal 214 of latch 202 is coupled to pixel electrode 204. A write signal on word line 138(r) places transistors 206 and 208 into a conducting state, causing the complementary data asserted on data lines 210(c) and 212(c) to be latched, such that the output terminal 214 of latch 202, and coupled pixel electrode 204, are at the same logic level as data line 210(c).
FIG. 3 shows an instruction table 300, which sets forth the op-code instructions used to drive display driver circuit 100. Each operation is explained with reference to FIG. 1. Op-code (00) corresponds to a No Op instruction, which is ignored by driver circuit 100. Op-code (01) is a Data Write command, which causes data being asserted on system data bus 126 to be loaded into write hold register 106. Op-code (11) is a Load Row Address command, which causes a row address being asserted on system data bus 126 to be loaded into row decoder 104. Op-code (10) is an Array Write command, which causes one line (1024 bits) of the data stored in write hold register 136 to be transferred to the latches of the row of pixel cells corresponding to the row address stored in row decoder 104.
FIG. 4 is a timing diagram showing how the above described op-codes are used to control driver circuit 100. During a first SCLK cycle, the system asserts a Data Write command (01) on op-code bus 128, causing a first 32-bit block (block 0) of data being asserted on system data bus 126 (D[31:0]) to be loaded into write hold register 106. During the next 31 SCLK cycles, the system asserts Data Write commands (01) causing 31 more 32-bit blocks to be loaded into write hold register 106, thus assembling a complete line of (1024) bits in write hold register 106. Next, the system asserts a row address (RA) on 10-bits of system data bus 126 (e.g., D)[9:0]) and a Load Row Address command (11) on op-code bus 128, loading the asserted address into row decoder 104. Finally, the system asserts a Array Write command (10) on op-code bus 128, causing the complete line of data in write hold register 106 to be loaded into a row of pixel cells of display 102 identified by the address in row decoder 104. This sequence is repeated to transfer each subsequent row of data from the system to display 102.
Prior art display driver 100 suffers from at least two disadvantages. First, because an entire row (1024 bits) of data is written to display 102 at once, driver circuit 100 and display 102 generate relatively large peak currents. Second, because a row address must be loaded prior to writing each line of data to display 102, driver circuit 100 has a relatively high system interface bandwidth requirement. Further, the peak current and the system bandwidth requirements are interrelated, in that writing data to smaller blocks of pixel cells at one time to reduce the peak current requirement increases the bandwidth requirement, because of the additional row addresses that must be loaded. What is needed is a display driver circuit with a reduced peak current requirement and a reduced system interface bandwidth requirement.